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Bug 564232 - Add cpu risc for RISC-V need to support.

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Change-Id: Ib62ed14f3c0dbe4375da41dba7209b27e034c53e
Signed-off-by: Aijun Shi <Aijun.Shi@windriver.com>
This commit is contained in:
Aijun Shi 2020-06-16 12:50:21 +08:00 • committed by Jonah Graham
parent 8b039257b7
commit 30845347d0
1 changed files with 6 additions and 0 deletions
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6
core/org.eclipse.cdt.core/utils/org/eclipse/cdt/utils/elf/Elf.java
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@ -158,6 +158,9 @@ public class Elf {
/** @since 6.0 */
public static final int EM_AARCH64 = 183;
/** @since 7.0 */
public static final int EM_RISCV = 243;
public static final int EM_NIOS = 0xFEBB;
public static final int EM_CYGNUS_POWERPC = 0x9025;
public static final int EM_CYGNUS_M32R = 0x9041;
@ -908,6 +911,9 @@ public class Elf {
case Elf.ELFhdr.EM_RS08:
attrib.cpu = "rs08"; //$NON-NLS-1$
break;
case Elf.ELFhdr.EM_RISCV:
attrib.cpu = "riscv"; //$NON-NLS-1$
break;
case Elf.ELFhdr.EM_NONE:
default:
attrib.cpu = "none"; //$NON-NLS-1$